This invention relates to a sequence control apparatus, and more particularly relates to a sequence control apparatus for providing a plurality of output signals selectively based upon either the rising edge of a clock signal or the falling edge of a clock signal.
State controllers are widely employed in electronic digital circuitry to determine and change the states of components of the circuitry with respect to the states of other components. One example of such circuitry is that which is used in control of memory devices, in which row address strobe, column address strobe and multiplex address switch signals are required. As the speed of operation of the circuitry increases, the need for higher speed in the operation of the state machine also increases, in order to provide a finer resolution for control of various components of the circuitry. One way in which this has been done is to employ a higher speed clock for the state machine. However this may not always be feasible to do, since such a clock may not be readily available, for reasons such as expense, reliability, difficulty of synchronization and power dissipation.